Join the global RISC-V community in Bologna, Italy from June 8–12, 2026 for keynotes, technical sessions, tutorials, and networking with leaders from semiconductors, AI, automotive, HPC, embedded systems, and more across the RISC-V ecosystem.
Reports
RISC-V Annual Report 2025
Read the RISC-V Annual Report to discover why 2025 was a defining year for the open standard ISA.
Events
RISC-V Summit North America 2025 On-Demand
Missed the action? Presentations are available to view on the RISC-V International YouTube Channel!
SPECIFICATION
The Technical Backbone of RISC-V
The RISC-V instruction set architecture (ISA) and related specifications are developed, ratified and maintained by contributing members within the Technical Working Groups. Download the latest releases, and get involved.
INDUSTRIES
RISC-V & Automotive
RISC-V is revolutionizing the automotive industry by providing a flexible and open architecture that enables customized, efficient computing solutions for advanced driver-assistance systems (ADAS) and autonomous vehicles.
INDUSTRIES
RISC-V & Artificial Intelligence
The RISC-V ISA is a common language for the development of AI systems, enabling a software based approach to hardware which unleashes a new level of compute and algorithm innovation, along with a better business case for bringing these new ideas to market.
Latest Blogs
Using a Performance Model to Implement a Superscalar CVA6Project Snapshot How does performance modeling accelerate real hardware innovation in open RISC-V designs? In this paper, Thales demonstrates a performance model of the CVA6 RISC-V processor, built to evaluate performance-related modifications before implementing them…
Production-Ready, Automotive-Grade, AI-Native: RISC-V at Embedded World 2026Ahead of Embedded World, we explore what our members and co-exhibitors will showcase in Nuremberg, the common threads linking their work, and what this reveals about the embedded landscape in 2026.
Support RAJA and Scientific Applications on RVV ArchitecturesProject Snapshot In this work, we aim to make RVV more accessible to scientific applications by integrating it into the RAJA performance-portability framework. RAJA is a C++ library primarily developed at Lawrence Livermore National Laboratory…
Get Started With Development
The RISC-V instruction set architecture (ISA) offers a highly customizable open standard platform, enabling developers to build, port, and optimize software applications, extensions, and hardware. Its simplicity and modularity enables efficient design and optimization, fostering innovation and reducing development time and cost.
I am Developing...
Support the Innovation of the RISC-V Architecture
Becoming a member of RISC-V International allows companies to actively influence the development of an open, royalty-free instruction set architecture, driving innovation in custom processor designs. Membership also provides access to a global community of experts and resources, fostering collaboration and accelerating product development.
Get Certified with RISC-V
RISC-V Fundamentals + Foundational Associate Exam Bundle
Designed for computer engineers and programmers to gain skills in RISC-V processors, enhancing your job market competitiveness. Essential learning experience for anyone looking to enhance their career in the tech industry.
